Transistor count, speed, power dissipation and layout considerations are typically the most important design criteria when designing logic circuits. CMOS circuits have an inherent power conservation characteristic over single conductivity MOS circuits and are therefore preferable when trying to minimize power consumption. An adder is a circuit which may be implemented with an exclusive OR/NOR circuit to effect an addition operation. A known technique to improve speed in circuits including adders is to increase the physical size of the transistors. However, this technique is not ideal since gate and source-to-drain capacitance of each transistor also increases which degrades speed performance. Since CMOS circuits have complementary transistors, capacitance is typically doubled as compared with single conductivity circuits and is further increased when transistor sizes are increased to improve speed. A known technique to obtain increased speed in an adder circuit is taught by Shively et al. in Transactions On Computers, Vol. C-33, No. 7, July 1984, pgs. 677-679, who teach the use of cascaded transfer logic (i.e. transmission gates) to improve the speed of an adder. Transmission gates provide less switching delay than inverting logic circuits. Kanapoulos et al. also teach a full adder circuit in "Design and Implementation of a CMOS Delta Modulator" in VLSI Design, February 1985, pgs. 98-101. The full adder taught by Kanapoulos et al. is implemented with an exclusive OR/NOR gate which uses transfer gates and inverters.